UE23CS251B: Microprocessor and Computer Architecture

This course will give you an in-depth understanding of the inner-workings of modern digital computer systems and trade-offs present at the hardware-software interface. The course focuses on key topics in microprocessor such as the system architecture, low level programming aspects and interface with other key components. Also, the course will help in understanding the core computer architecture concepts such as multilevel in memory hierarchies, pipelining, and super scalar techniques.

Course Objectives

  • Introduce concepts of basic processor architecture and its design.
  • Understanding the concept of concepts of pipeline architecture and hazards.
  • Study of memory hierarchy, cache memory and its optimizations.
  • Introduce advanced concepts in processor architecture like multi-core/ many core processor architectures.

Course Outcomes

At the end of the course, the student will be able to:

  • Demonstrate ability to understand the design of different instruction sets like RISC/ CISC and their addressing modes.
  • Demonstrate the ability to understand the design of a pipelined processor and its challenges.
  • Demonstrate the use of tools to analyse the performance of programs on different architectures. Design alternative memory hierarchy layouts and optimizations.
  • Demonstrate and appreciate modern trends in architecture such as multicore architectures.

Course Content

U1: Architecture

Introduction, ISA Classification - RISC and CISC, Memory Addressing, Operands - Types and Size, Instruction Set, Operations, Control Flow, Instruction Encoding, Case Study - ARM/ MIPS/ x86 Processor.

U2: Pipelining

3- Stage Pipelining, 5 - Stage Pipelining, Pipeline Datapath and Control, Data Hazards – Forwarding vs. Stalling, Control Hazards, Branch Prediction Mechanisms and Exceptions, Performance Metrics.

U3: Basics of Cache and Cache Optimization

Basics of Caches - Fully Associative, Direct Mapped and Set Associativity, Cache Performance, Basic Cache Optimization- Reduce in Miss Rate. Basic Cache Optimization- Reduce Miss Penalty, Reduce Hit Time.

U4: Advances in Architecture

Introduction to Parallel Computing, PC – Applications, Memory architecture, Flynn’s taxonomy, parallel programming models, Shared memory programming OpenMP-Introduction, loop-level parallelism, CUDA C Program structure-vector kernel addition, device global memory and Data transfer, Hardware Multi threading, Parallel examples: matrix multiplication, PC-Design Issues, Amdahl’s Law, Gustafson Law, Multi-Core Architecture, Introduction to GPU computing


prerequisites: UE23CS251B